Reduction of Power Consumption for Pipelined DPI Systems on FPGA

We propose a scheme to reduce power consumption in pipelined AC-DFA (Aho-Corasick deterministic finite automaton) tries for deep packet inspection (DPI). It is based on our observation that the access frequency drops dramatically as the input goes through stages of the pipelined implementation of the AC-DFA trie. Experiments show that the access frequency of the fourth stage is one thousandth of the access frequency of the first stage. So, we slow down the stages that are not frequently used in the pipelined AC-DFA trie to reduce unnecessary power consumption. Also, we turn on the next stage before a stage performs a pattern matching, to reduce delays and clock skew without any additional hardware components. Our scheme shows a 25% reduction in power consumption, compared with the state-of-the-art DPI scheme [3] with a pipelined AC-DFA trie.