Speed and power comparison of CMOS wave pipelined systems and low power WTGL

被引：0
|
作者：
Sridhar, R [1 ]
MartinezSmith, A [1 ]
McGee, B [1 ]
机构：
[1] SUNY BUFFALO,DEPT ELECT & COMP ENGN,BUFFALO,NY 14260
来源：
ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4 | 1996年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：156 / 159
页数：4
相关论文
共 50 条
  • [1] High-speed low-power CMOS pipelined analog-to-digital converter
    Ju, RA
    Lee, DH
    Yu, SD
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1999, E82A (06) : 981 - 986
  • [2] CMOS dynamic comparator for pipelined ADCs with improved speed/power ratio
    Liu, Ke
    Yang, Haigang
    [J]. Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 2008, 29 (01): : 75 - 81
  • [3] The design of low-power CMOS pipelined-burst SRAM
    Lee, CL
    Wagiran, R
    Suprajo, BS
    Sidek, R
    [J]. 2000 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2000, : 241 - 244
  • [4] A high speed and low power CMOS current comparator for photon counting systems
    Borghetti, F
    Farina, L
    Malcovati, P
    Maloberti, F
    [J]. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, 2004, : 453 - 456
  • [5] Low Power and High Speed CMOS Current Comparators
    Nasir, Wan Irma Idayu Restu Binti Wan Mohd
    Reaz, Md Mamun Bin Ibne
    [J]. 2016 INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRICAL, ELECTRONIC AND SYSTEMS ENGINEERING (ICAEES), 2016, : 539 - 543
  • [6] A High Speed Low Power Pipelined SAR Analog to Digital Converter
    Kuo, Ko-Chi
    [J]. 17TH IEEE INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2019), 2019,
  • [7] A High-Speed Low-Power Flash ADC with Continued Pipelined Gating in 28-nm CMOS
    Gao, Yu Miao
    Qiu, Lei
    Guo, Xin Yu
    Tong, Mei Song
    [J]. 2020 IEEE MTT-S INTERNATIONAL CONFERENCE ON NUMERICAL ELECTROMAGNETIC AND MULTIPHYSICS MODELING AND OPTIMIZATION (NEMO 2020), 2020,
  • [8] A CMOS 10-bit low-power pipelined A/D converter
    Dai, GD
    Liu, F
    Zhuang, YQ
    [J]. 2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 1563 - 1566
  • [9] Low-Power High-Speed On-Chip Asynchronous Wave-pipelined CML SerDes
    Jaiswal, Ashok
    Walk, Dominik
    Fang, Yuan
    Hofmann, Klaus
    [J]. 2014 27TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2014, : 5 - 10
  • [10] Performance analysis of low power high speed pipelined adders for digital ΣΔ modulators
    Bhansali, P.
    Hosseini, K.
    Kennedy, M. P.
    [J]. ELECTRONICS LETTERS, 2006, 42 (25) : 1442 - 1444
12345