Modeling the temperature distribution of multi-chip integrated circuits combining Wire-Bond and Flip-Chip technologies

被引:0
|
作者
Boriskov, P. P. [1 ]
Ershova, N. Yu [1 ]
Putrolaynen, V. V. [1 ]
Seredov, P. N. [1 ]
Belyaev, M. A. [1 ]
机构
[1] Petrozavodsk State Univ, Inst Phys & Technol, 33 Lenin Str, Petrozavodsk 185910, Russia
关键词
D O I
10.1088/1742-6596/1399/2/022036
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
On the basis of finite-element computer modeling, the temperature distribution of a multi-chip integrated circuit was calculated in System on Package configuration, combining Wire-Bond and Flip-Chip technologies. Technical recommendations are suggested for choosing a compound, taking into account the continuous layer of the compound separating the active elements and the heat sink.
引用
收藏
页数:5
相关论文
共 50 条
  • [31] Small-size temperature/high-pressure integrated sensor via flip-chip method
    Huang, Mimi
    Wu, Xiaoyu
    Zhao, Libo
    Han, Xiangguang
    Xia, Yong
    Gao, Yi
    Cui, Zeyu
    Zhang, Cheng
    Yang, Xiaokai
    Qiao, Zhixia
    Li, Zhikang
    Han, Feng
    Yang, Ping
    Jiang, Zhuangde
    MICROSYSTEMS & NANOENGINEERING, 2024, 10 (01):
  • [32] The Effects of Die Thickness and Bond Height on Wire Sweep in Multi-Chip Module and 3-Dimennsional Packages
    Chen, H. -S.
    Huang, C-B.
    Kung, H. -K.
    2008 EMAP CONFERENCE PROCEEDINGS, 2008, : 204 - 207
  • [33] The Demonstration of Carbon Nanotubes (CNTs) as Flip-Chip Connections in 3-D Integrated Circuits With an Ultralow Connection Resistance
    Liao, M-H
    Lu, P-Y
    Su, W-J
    Chen, S-C
    Hung, H-T
    Kao, C-R
    Pu, W-C
    Chen, C-C A.
    Lee, M-H
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (05) : 2205 - 2207
  • [34] The influence of external factors on the temperature distribution of flip-chip package - Comparative Analysis between Flotherm and Abaqus
    Jiang, Ruoyu
    Zhong, Cheng
    Li, Chenglong
    Li, Yulong
    Peng, Xu
    Lu, Jibao
    Sun, Rong
    2022 23RD INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT, 2022,
  • [35] Modeling Temperature Distribution in Networks-on-Chip using RC-Circuits
    Tockhorn, Andreas
    Cornelius, Claas
    Saemrow, Hagen
    Timmermann, Dirk
    PROCEEDINGS OF THE 13TH IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2010, : 229 - 232
  • [36] Wafer Bumping Process and Inter-Chip Connections for Ultra-High Data Transfer Rates in Multi-Chip Modules With Superconductor Integrated Circuits
    Tolpygo, Sergey K.
    Tolpygo, Diana
    Hunt, Richard T.
    Narayana, Supradeep
    Polyakov, Yuri A.
    Semenov, Vasili K.
    IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2009, 19 (03) : 598 - 602
  • [37] Time evolution of temperature distribution of a flip-chip no-flow underfill package during solder reflow process
    Zhang, ZQ
    Vorakunpinij, A
    Sitaraman, SK
    Wong, CP
    53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS, 2003, : 443 - 448
  • [38] CHARACTERIZATION AND MODELING OF SCHOTTKY DIODES UP TO 110 GHz FOR USE IN BOTH FLIP-CHIP AND WIRE-BONDED ASSEMBLED ENVIRONMENTS
    Zeljami, K.
    Gutierrez, J.
    Pascual, J. P.
    Fernandez, T.
    Tazon, A.
    Boussouis, M.
    PROGRESS IN ELECTROMAGNETICS RESEARCH-PIER, 2012, 131 : 457 - 475
  • [39] SAM Interpretation of Interfacial Anomaly in Flip-Chip BGA Package with 65nm Cu/Low-κ Integrated Circuits Device
    Lee, Ka Yau
    Lee, Priscilla
    Tan, Ai Min
    Lee, Charles
    IEMT 2006: 31ST INTERNATIONAL CONFERENCE ON ELECTRONICS MANUFACTURING AND TECHNOLOGY, 2006, : 269 - 274
  • [40] Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multi-layer ceramic BGA
    Libous, JP
    OConnor, DP
    ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING - IEEE 5TH TOPICAL MEETING, 1996, : 120 - 122