An FPGA hardware implementation of the Rijndael block cipher

被引：0

作者：

Dhoha, Chorfi

Ben Othman, Slim

Ben Saoud, Slim

机构：

来源：

IEEE DTIS: 2006 International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Proceedings | 2006年

关键词：

AES; Rijndael; encryption; decryption; hardware implementation;

D O I：

10.1109/DTIS.2006.1708717

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a hardware implementation of an Advanced Encryption Standard (AES) Rijndael (128-bit block and 128-bit key) using Xilinx development tools and Spartan FPGA circuits. All the modules in this core are described by using VHDL language. The developed Rijndael core is aimed at providing sufficient performance with good area efficiency. In fact, the encryption/decryption data path operates at 29,29,45MHz resulting in a throughput of 289,98 Mbits per second for the encryption and 157,1 Mbits per second for decryption. Encryption/decryption circuit will fit in one Xilinx Spartan XC2S600E circuit taking approximately 87% of the area (6068 Slices). Compared to software implementation, migrating to hardware provides higher level of security and faster encryption speed.

引用

页码：351 / 354

页数：4

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