Output-Capacitor-Less LDO with High PSR

A low-dropout regulator (LDO) with high power supply ripple rejection (PSR) and capacitor-free is presented in this paper. The LDO proposes a PSR enhancement module based on the analysis of the power supply noise transmission path. It uses the Q-reduction circuit to reduce the required on-chip capacitor and the load on the minimum required output. The proposed LDO is implemented in 110 nm CMOS process. The simulation results indicate that the total on-chip capacitance required for the designed circuit is 6.5 p. The LDO has a phase margin of more than 60 in the range of 50uA to 50 mA. The optimum PSR of the LDO at low frequency is -109 dB. The LDO achieves line and load regulation of 65 mu V/V and 0.396 mu V/mA respectively.