AN OPTIMIZED DESIGN OF REVERSIBLE MAGNITUDE AND SIGNED COMPARATORS

Reversible logic has gained significant prominence in recent years due to its wide spread application in quantum computing. The major advantage of reversible logic circuit over conventional logic circuits is reduced heat losses during computation. Comparators are widely used in digital communication devices, encryption devices, sorting networks, data converters, address decoding circuitry in computers etc., This paper proposes designs of magnitude and signed comparators designed using standard reversible gates such as Fredkin, Feynman and Peres gates. Multiple performance parameters are optimized with emphasis given to delay optimization. The generalized design methodologies for N bit comparators are also proposed and design metrics are compared with existing state-of-the-art work. The proposed designs shows improved performance in comparison with the existing designs in literature.