A parallel hardware evolvable computer POLYP - Extended abstract

Previous work has shown the power of massively parallel configurable hardware (NGEN, [1, 2]) in conjunction with dataflow architectures for the simulation of evolving populations. NGEN is a flexible computer hardware for rapid custom-circuit simulation of fine grained physical processes via a massively parallel architecture, e. g. 144 hardware configurable field programmable gate arrays (FPGAs, XC4008, Xilinx). NGEN is optimized to implement dataflow architectures and systolic algorithms for large problems and is confectioned with high speed distributed SRAM, 144*8*256kBit -15ns access time, on the chip-to-chip interconnect.Micro-configurable FPGAs allow a further step to close the gap between micro electronics and biology on the information processing area. A design for a massively parallel micro configurable computer (POLYP) is presented. It is designed to allow online evolution in hardware with significant locally controllable memory resources. It is also designed for high througput dataflow applications with large problem size. Additionally, an evolvable interface between high rate measurement devices is provided to allow adaptive processing coupled with real time experimental environments. The computer represents the next logical step, towards evolvable hardware interacting with biology beyond the massively parallel computer NGEN. The computer is embedded in a standard VME64 bus system and operated with a classical Unix workstation host and the superimposed operating system written for NGEN. One challenge in conjunction with evolvable hardware in optimisation scenarios is to obtain a microscopic feedback between processed information and the reconfiguration of the hardware. The reconfiguration of the logic in NGEN can only proceed at the whole chip level and is relatively slow, taking a few tenths of a second. A new generation of micro-configurable chips (Xilinx XC6200 FPGAs), in which the configuration data is individually addressable bike SRAM, has been utilized to design a second generation micro-configurable hardware computer [3]. The Xilinx XC6200 FPGAs have already been used for analog evolution in hardware. The hardware cards of POLYP are in 18 multilayer technology and wherever possible the parts are surface mounted. Four optical interface chips (Optobus, Motorola) are connected via two crossbars to the eight agent FPGAs of type Xilinx XG6200. All agent FPGAs are temperature supervised and can be shutdown each in case of over-heating. Two distributer FPGAs (XC4028) mediate the dynamic reconfiguration cycle and host communication of the agent FPGAs, see fig. 1. These communicate with the host workstation via a control FPGA (XC4028) and an optimised design FPGA (XC4006) implementing the VME64 standard. Distributed SRAM is provided as in NGEN, 6 Mbit per agent FPGA, 4 Mbit per distributor FPGA and control FPGA. Further details may be found in [3].