An asymmetrical multilevel inverter topology with reduced source count

被引：0
|
作者：
Reddy, K. Raghavendra [1 ]
Sabyasachi, Sidharth [1 ]
Meshram, P. M. [2 ]
Borghate, V. B. [1 ]
机构：
[1] Visvesvaraya Natl Inst Technol, Dept Elect Engn, Nagpur, Maharashtra, India
[2] Yeshwantrao Chavan Coll Engn, Dept Elect Engn, Nagpur, Maharashtra, India
来源：
2016 IEEE STUDENTS' CONFERENCE ON ELECTRICAL, ELECTRONICS AND COMPUTER SCIENCE (SCEECS) | 2016年
关键词：
Multilevel inverters; Asymmetrical topologies; Total harmonic distortion; H-bridge; H-BRIDGE INVERTER; INDUSTRIAL APPLICATIONS; MODULATION TECHNIQUE; CONVERTER; SYSTEM; NUMBER; PERFORMANCE; SWITCHES;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, an asymmetrical topology for cascaded multilevel inverter based on basic converter unit, series unit and full-bridge is proposed. It offers lower total harmonic distortion, switching losses and voltage stress on switches than conventional inverters. An algorithm to determine dc voltage sources magnitudes is proposed. The gating signals for the power switches are generated by employing Nearest Level Control (NLC) method. This structure allows a reduction of the system cost and size. Effectiveness of the proposed topology has been demonstrated by analysis and simulation.
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页数：6
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