A single-chip MPEG-2 codec based on customizable media microprocessor

被引：6

作者：

Ishiwata, S ^{[1
]}

Yamakage, T ^{[1
]}

Tsuboi, Y ^{[1
]}

Shimazawa, T ^{[1
]}

Kitazawa, T ^{[1
]}

Michinaka, S ^{[1
]}

Yahagi, K ^{[1
]}

Takeda, H ^{[1
]}

Oue, A ^{[1
]}

Kodama, T ^{[1
]}

Matsumoto, N ^{[1
]}

Kamei, T ^{[1
]}

Miyamori, T ^{[1
]}

Ootomo, G ^{[1
]}

Matsui, M ^{[1
]}

机构：

[1] Toshiba Co Ltd, Syst LSI Res, Kawasaki, Kanagawa 2128520, Japan

来源：

PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2002年

关键词：

D O I：

10.1109/CICC.2002.1012789

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on 72mm(2) die, is described. It has heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video, audio etc. concurrently. The microprocessor, developed for digital media processing, provides various extensions such as VLIW one and DSP one inherent in its architecture. Making full use of the extensions, the chip executes encoding and decoding of video, audio and system concurrently in real time.

引用

页码：163 / 166

页数：4

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