Process-Design Co-Optimization for FPGA

被引：0
|
作者：
Xiang, Qi [1 ]
机构：
[1] Altera Corp, San Jose, CA 95134 USA
来源：
2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4 | 2008年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Advancement of field programmable gate array (FPGA) faces many challenges. Among the major ones are power management and high speed transceiver I/O demands. To overcome the challenges, process-design co-optimization is required. With co-optimization of process, circuit, and architecture, 45% static power reduction is achieved for a 40nm FPGA design. With optimized analog devices, high data rate (8.5Gbps) transceivers are produced using a 40nm digital process.
引用
收藏
页码：2031 / 2034
页数：4
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