Hardware efficient architecture for compressed imaging

Compressed sensing has gained a wide application in image acquiring and reconstructing. Separable linear reconstruction has been shown to be effective in compressed imaging. This paper presents efficient hardware architecture based on adaptive sampling and separable reconstructing. By exploiting parallel properties in the architecture and timing scheme, high performance hardware has been proposed for both encoding and decoding sides. High performance Cholesky based matrix inversion has been implemented to solve the least square problem. Besides, high precision arithmetic element functions (reciprocal and square root reciprocal) have been presented by using of table interpolation and single iterated Newton-Raphson method. Experiment results show that the proposed hardware architecture can efficiently reduce the process time in encoding and decoding of a 512 x 512 image. The speedup is about 58x compared with the software-based approach (using LAPACK), and it is at least 1.92x faster than the state-of-the-art implementation.