Design and Analysis of a Hardware-efficient Compressed Sensing Architecture for Data Compression in Power Quality Data Acquisition

In this paper, power quality disturbances are sampled by an under-sampling compressed sensing (CS) system. The random demodulator is modeled and the mathematical expressions of random sequence, mixer and integrator are derived. Based on the model, random demodulator architecture for power quality data acquisition including control, sampling and communication circuit is designed and realized. The hardware platform is built with implementation of pseudo random sequence, sampling program data cache and serial communication control in FPGA. When the input power quality signal contains fundamental and oscillating voltage with a frequency of 4kHz, design a random demodulator with a ADC sampling frequency of 2kHz, observe the waveform at each part of the random demodulator and analyze the reconstruction results. The time-domain waveform and spectrum analysis results show that the designed architecture retains the information of fundamental frequency and high frequency oscillation which verify the effectiveness of the designed schemes