An Efficient Hardware Architecture for Lossless Data Compression in Data Center

Data compression algorithms with high compression ratio are vital to modern data centers due to limited bandwidth and the exponential increases in the quantity of data stored. PAQ is the collection of a series of open source compression algorithms ranking top in terms of compression ratio on many typical benchmarks. Due to its high computational complexity and large memory usage, PAQ is not widely used. In this paper, based on a lite version of PAQ (LPAQ1) algorithm, an improved LPAQ1 (ILPAQ1) algorithm is presented to reduce the memory usage and improve the throughput at the cost slightly loss in the compression ratio. For the ILPAQ1 algorithm, the tradeoff between compression ratio and memory usage is also investigated based on some typical benchmarks. To the best of our knowledge, for the first time, a well-optimized VLSI architecture for the predictor part, which dominates the overall complexity of the ILPAQ1 algorithm, is proposed. The predictor architecture is coded in RTL and synthesized under the TSMC 90mn CMOS technology. The implementation results demonstrate that the proposed architecture achieves a throughput of 44.4 Mb/s at 400MHz clock speed, which is 5 times faster than that of the software implementation based on Intel core-i7 4790 CPU at 3.60 GHz.