Gbit/s lossless data compression hardware

被引：35
|
作者：
Núñez, JL
Jones, S
机构：
[1] Univ Loughborough, Dept Elect & Elect Engn, Loughborough LE11 3TU, Leics, England
[2] Univ Bath, Dept Engn & Design, Bath BA2 7AY, Avon, England
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2003年 / 11卷 / 03期
关键词：
data compression; field-programmable gate arrays (FPGAs); lossless circuits;
D O I：
10.1109/TVLSI.2003.812288
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents the X-MatchPRO high-speed lossless data compression algorithm and its hardware implementation, which enables data independent throughputs of 1.6 Gbit/s compression and decompression using contemporary low-cost reprogrammable field-programmable gate array technology. A full-duplex implementation is presented that allows a combined compression and decompression performance of 3.2 Gbit/s. The features of the compression algorithm and architecture that have enabled the high throughputs are described in detail. A comparison between this device and other commercially available data compressors is made in terms of technology, compression ratio, and throughput. X-MatchPRO is a fully synchronous design proven in silicon specially targeted to improve the performance of Gbit/s storage and communication applications.
引用
收藏
页码：499 / 510
页数：12
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