A Fast Compressed Hardware Architecture for Deep Neural Networks

Hardware acceleration of Deep Neural Networks (DNNs) is very critical to many edge applications. The acceleration solutions available today are typically for GPU, CPU, FPGA and ASIC platforms. The Single Partial Product 2-D Convolution known as SPP2D is a hardware architecture for fast 2-D convolution which can be used for implementing a convolutional neural network (CNN). The SPP2D based CNNs prevent the re-fetching of input pixels for the calculation of partial products and it computes the output for any input size and kernel with low latency and low power consumption compared to some other popular techniques. SPP2D based VGGNet-16 rivals the performance of other existing implementations as well as a FIFO based CNN architecture which takes a novel approach to compute convolution results using row-wise inputs as opposed to traditional tile-based processing. In this paper, we present an SPP2D based hardware accelerator for a channel compressed network. We find that the low power SPP2D implementation gives a better performance in terms of low power and low execution time compared to other compressed contemporary designs. A compressed network requires less on-chip memory thus reducing the most power consuming task of moving data from off-chip to on-chip. This results in a considerable reduction in power consumption due to the reduction in memory traffic. Channelpruned SPP2D accelerator is a low power design of 298 mW which is about 0.01x to 0.37x of the existing works while also having a low execution time of 0.9 secs.