An 8-bit parallel DAC with segmented architecture

被引：7

作者：

Enuchenko, M. S. ^{[1
]}

Morozov, D. V. ^{[1
]}

Pilipko, M. M. ^{[1
]}

机构：

[1] Peter Great St Petersburg Polytech Univ, Politekhnicheskaya Ul 29, St Petersburg 195251, Russia

来源：

JOURNAL OF COMMUNICATIONS TECHNOLOGY AND ELECTRONICS | 2017年 / 62卷 / 01期

关键词：

D O I：

10.1134/S1064226917010053

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An 8-bit parallel DAC with a segmented architecture that employs a 4-bit binary and an unary segments is presented. A switched current source and a thermometric decoder are discussed. A test chip is fabricated using a 180-nm CMOS technology. Measured results show higher conversion rate and smaller chip area in comparison with other papers.

引用

页码：89 / 100

页数：12

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