Evolutionary Computation on Coarse-Grain Reconfigurable Architecture

System-on-chip (SOC) evolution is demonstrated on commercial field programmable gate arrays. A coarse-grain reconfigurable architecture is proposed based on the system-on-programmable-chip (SOPC) technology, which is expected to bring benefits to applications of spacecraft survivability. The distributed architecture inherently makes it a suitable candidate for fault-tolerant design. The fault-tolerant ability originates from the many approaches of an algorithm to be mapped onto the evolvable chip: new hardware configurations can be synthesized to provide required functionality and existing function can be preserved in condition where the hardware is subject to faults. The architecture is implemented on Altera Cyclone II 2C35 using DE2 board.