Low leakage and high performance tag comparator implemented in 180nm CMOS technology

The parasitic capacitance in the dynamic node increases for wide tag comparator increasing the delay and power consumption. The output signal may also degrade with high performance computing that uses clock frequency over 1GHz. In this paper a circuit is proposed to reduce the delay of the evaluation phase of the 64 bit tag comparator by reducing the parasitic capacitance at the dynamic node. The circuit is applicable for wide fan-in gates. The performance has enhanced by 60-70% with reduced leakage providing reduced voltage degradation of the output signal when compared to the rest of the dynamic circuit under study. The Mentor Graphics tool kit is used to perform pre-layout simulations, circuit layout generation and physical verification of the layout. (C) 2015 The Authors. Published by Elsevier B.V.