FPGA implementation of programmable pulse mode neural network with on chip learning

被引：2

作者：

Damak, Alima ^{[1
]}

Krid, Mohamed ^{[1
]}

Masmoudi, Dorra Sellami ^{[1
]}

Derbel, Nabil

机构：

[1] Univ Sfax, Res Unit Intelligent Control Design & Optimisat C, Sfax Engn Sch, BP W 3038, Sfax, Tunisia

来源：

IEEE DTIS: 2006 INTERNATIONAL CONFERENCE ON DESIGN & TEST OF INTEGRATED SYSTEMS IN NANOSCALE TECHNOLOGY, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/DTIS.2006.1708686

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an implementation of a pulse mode multilayer neural network with on chip learning. Taking advantage of the compactness of the multiplierless solutions proposed in the literature, we apply a multiplieriess architecture, in which the synapse is made up with a DDFS and the neuron uses a nonlinear adder. A programmable activation function is proposed by means of an adjustable pulse multiplier so that the activation function slope can he adjusted without any added hardware cost. The proposed architecture was tested in a signature recognition system. It shows good learning capability. The corresponding design was implemented into a virtex II PRO XC2VP7 Xilinx FPGA.

引用

页码：159 / 164

页数：6

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