A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme

被引：0
|
作者：
Guo, Yuekang [1 ,2 ]
Liu, Xiaoming [2 ]
Jin, Jing [2 ]
Zhou, Jianjun [1 ,2 ]
机构：
[1] Shanghai Jiao Tong Univ, AI Inst, MoE Key Lab Artificial Intelligence, Shanghai, Peoples R China
[2] Shanghai Jiao Tong Univ, Ctr Analog RF Integrated Circuit CARFIC, Dept Micronano Elect, Shanghai, Peoples R China
来源：
2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22) | 2022年
关键词：
SAR ADC; offset calibration; asynchronous logic; multibit/cycle; ping-pong operation;
D O I：
10.1109/ISCAS48785.2022.9937630
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a 3bit/cycle 1GS/s 8-bit SAR ADC with asynchronous ping-pong quantization scheme. With the proposed scheme, settling requirement of the reference voltages for multibit quantizer can be relaxed. In addition, loop-unrolled technique can be easily embedded in the SAR logic for higher speed without extra hardware consumption. Moreover, using the ping-pong scheme, the comparator offset can be corrected in background mode without extra calibration phase. The ADC is designed and simulated in 22nm CMOS process. Without calibration, the ADC achieves 33.4 dB SNDR. With offset calibration, the SNDR can be improved to 47.2 dB.
引用
收藏
页码：2650 / 2654
页数：5
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