Design of a GHz high speed memory system

Digital application has moved towards operating speed of hundreds of Mega Hertz, with the sampling speed of ADC moving into Giga Hertz range. There is an increasing need for the design and development of a high-speed data acquisition system that is capable of capturing and processing digitised analogue signal at high speed. Due to the light timing budget, high operating speed components, Emitter-Coupled-Logic (ECL) families components with rise time of typically less than 300ps were used in the design. With this operating speed and short rise time, signal integrity issues like reflections due to impedance mismatches and crosstalk among the traces of the printed circuit board can no longer be neglected. A quick and reliable approach was taken in the design and implementation of a 1 GHz high-speed data acquisition system using commercial-off-the-shelf (COTS) discrete components. High-speed digital design issues and methodology were explored in this project and verified with the implemented hardware. This paper gives an overview of the system and focuses on the use of functional and signal-integrity computer simulation software to confirm system performance at the early design stage before actual hardware implementation. Simulation results were further confirmed with the actual hardware implemented, and was found to be close. This has helped to reduce the design cycle time and development cost of the project.