DESIGN OF HIGH-SPEED BIPOLAR MEMORY LSI

被引：0
|
作者：
HOMMA, N
INADACHI, M
YAMAGUCHI, K
KITSUKAWA, G
机构：
来源：
ELECTRONICS & COMMUNICATIONS IN JAPAN | 1977年 / 60卷 / 12期
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：94 / 102
页数：9
相关论文
共 50 条
  • [1] HIGH-SPEED BIPOLAR LOGIC LSI
    SUDO, T
    NAKASHIMA, T
    YOSHII, A
    [J]. REVIEW OF THE ELECTRICAL COMMUNICATIONS LABORATORIES, 1979, 27 (1-2): : 55 - 71
  • [2] AN ADVANCED PSA TECHNOLOGY FOR HIGH-SPEED BIPOLAR LSI
    NAKASHIBA, H
    ISHIDA, I
    AOMURA, K
    NAKAMURA, T
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (08) : 1390 - 1394
  • [3] AN ADVANCED PSA TECHNOLOGY FOR HIGH-SPEED BIPOLAR LSI
    NAKASHIBA, H
    ISHIDA, I
    AOMURA, K
    NAKAMURA, T
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (04) : 455 - 459
  • [4] A NEW TRANSISTOR STRUCTURE FOR HIGH-SPEED BIPOLAR LSI
    SAKURAI, H
    AKASAKA, Y
    MURAKAMI, K
    KIJIMA, K
    NAKATA, H
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS, 1980, 19 : 181 - 185
  • [5] VERY HIGH-SPEED BIPOLAR LSI PROCESS TECHNOLOGY - SST
    SAKAI, T
    KONAKA, S
    YAMAMOTO, Y
    [J]. REVIEW OF THE ELECTRICAL COMMUNICATIONS LABORATORIES, 1987, 35 (04): : 359 - 364
  • [6] DESIGN CONSIDERATIONS FOR A HIGH-SPEED BIPOLAR READ-ONLY MEMORY
    BARRETT, JC
    BERGH, A
    HORNAK, T
    PRICE, JE
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1970, SC 5 (05) : 196 - &
  • [7] DESIGN AND PROCESSING FOR HIGH-SPEED SHORT CHANNEL CMOS LSI
    OHWADA, K
    EHARA, K
    OMURA, Y
    DOKEN, M
    [J]. REVIEW OF THE ELECTRICAL COMMUNICATIONS LABORATORIES, 1979, 27 (7-8): : 642 - 648
  • [8] High-speed bipolar MUX modeling and design
    Alioto, M
    Palumbo, G
    [J]. ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 1 - 4
  • [9] HIGH-SPEED BIPOLAR RANDOM ACCESS MEMORY SERIES.
    Ogiue, Katsumi
    Oowaki, Seishirou
    [J]. Hitachi Review, 1980, 29 (03): : 115 - 118
  • [10] DESIGN FOR A HIGH-SPEED MOS ASSOCIATIVE MEMORY
    LEA, RM
    [J]. ELECTRONICS LETTERS, 1972, 8 (15) : 391 - +
12345