Ultralow-power CMOS/SOI LSI design for future mobile systems

被引:11
|
作者
Douseki, T [1 ]
Yamada, J [1 ]
Kyuragi, H [1 ]
机构
[1] NTT Corp, NTT Telecommun Energy Labs, Atsugi, Kanagawa, Japan
关键词
D O I
10.1109/VLSIC.2002.1015028
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Ultralow-power CMOS/SOI circuit technology that uses fully-depleted SOI and multi-threshold (MT) CMOS circuits makes it possible to lower the supply voltage to 0.5 V and reduce the power dissipation of LSIs to 1 similar to 10 mW without any speed loss. We overview the ultralow-power CMOS/SOI circuit technology and some ultralow-voltage LSIs based on MTCMOS/SOI circuits.
引用
收藏
页码:6 / 9
页数:4
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