A 75 μW Two-Stage Op-Amp using 0.18 μW CMOS Technology for High-Speed Operations

被引：2

作者：

Shashidhar, K. ^{[1
]}

Ijjada, Sreenivasa Rao ^{[2
]}

Naresh, B. ^{[2
]}

机构：

[1] Guru Nanak Inst Tech Campus, Dept Elect & Commun Engn, Ibrahimpatnam, Telangana, India

[2] GITAM Univ, Dept Elect & Commun Engn, Visakhapatnam, Andhra Pradesh, India

来源：

ACTA PHYSICA POLONICA A | 2019年 / 135卷 / 05期

关键词：

D O I：

10.12693/APhysPolA.135.1075

中图分类号：

O4 [物理学];

学科分类号：

0702 ;

摘要：

Low voltage operated Analog and digital circuits have big demand due to its better performance. But, it leads to number of challenges. Operational amplifier is the basic element in most of the circuits, because of its wide advantages. Gain, bandwidth, linearity, noise and output swings are the design parameters. Operational amplifier design is unique for different applications. This paper presents the design of a 1.8V two-stage Operational amplifier using 0:18 mu m CMOS technology for low power and high-speed operations. This design draws 5 mu A current with 1.8 V and produced the gain of 87 dB, phase margin (PM) of 67 degrees and the unity gain bandwidth (GBW) of 4.87 MHz through AC analysis. The proposed design has a Slew rate of 4.126 V/mu s, which determines the speed of the Operational amplifier. The input common mode range (ICMR) is improved to 0.07-1.65 V and the power dissipation is 75 mu W.

引用

页码：1075 / 1077

页数：3

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