A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application

被引：7
|
作者：
Liu, Maliang [1 ]
Li, Dengquan [1 ]
Zhu, Zhangming [1 ]
机构：
[1] Xidian Univ, Shaanxi Key Lab Integrated Circuits & Syst, Sch Microelect, Xian 710071, Peoples R China
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2020年 / 67卷 / 04期
基金：
中国国家自然科学基金;
关键词：
Bandwidth; Gain; Operational amplifiers; Pipelines; MOSFET; Pipeline ADC; dual-supply op-amp; single channel; INTERLEAVED SAR ADC; SNDR; 1-GS/S;
D O I：
10.1109/TCSII.2019.2926133
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this brief, a dual-supply two-stage op-amp is proposed for a 12-b 1 GS/s pipeline ADC, which is composed of a low-voltage supply pre-amplifier and a high-voltage supply amplifier. Its closed-loop bandwidth reaches to 5.2 GHz, and the phase margin is larger than 60 degrees. The closed-loop amplifier can settle to 99.95% accuracy within 230 ps, which satisfies the harsh requirements of the first-stage MDAC. The proposed op-amp was employed in a single-channel 12-b 1 GS/s pipeline ADC. The ADC is powered by 1.3 V and the op-amp is powered by dual-supply voltage of 1.3 V and 2.5 V. The ADC fabricated in 65 nm CMOS process consumes 360 mW at 1 GS/s. It achieves an SNDR of 61.9 dB and an SFDR of 72.6 dB with 30 MHz input signal, while maintaining an SNDR > 56.0 dB and SFDR > 69.0 dB in the entire 500 MHz Nyquist band.
引用
收藏
页码：650 / 654
页数：5
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