Minimizing Temperature Nonuniformity by Optimal Arrangement of Hotspots in Vertically Stacked Three-Dimensional Integrated Circuits

The semiconductor packaging technologies have seen its growth from multichip module (MCM), system in package (SiP), system on chip (SoC) to the heterogeneous integration of the MCM. Thermal management of multichip vertically integrated systems poses additional constraints and limitations beyond those for single chip modules. Three-dimensional-integrated circuits (3D ICs) technology is a potential approach for next-generation semiconductor packaging technologies. A 3D IC is formed by vertical interconnection of multiple substrates containing active devices which offer reduced die footprint and interconnect length. This paper discusses the optimal arrangement of two hotspots on each layer of a two-die stacked 3D IC. An analytical heat transfer model for prediction of three-dimensional temperature field of a 3D IC based on the solution of governing energy equations has been developed and used for this study. The model is subject to adiabatic boundary conditions at the walls except for the bottom wall which is subject to convective boundary condition. A feed-forward back propagation artificial neural network (ANN) is employed for obtaining the functional relationship between the location of the hotspots and the objectives. Genetic algorithm is employed for solving two nonconflicting objective functions subject to set of constraints. The first objective aims to minimize the maximum temperature on both layers, and the second objective aims to achieve temperature uniformity in the layers. The results of the optimization study are expected to provide recommendations on the design guidelines for arranging hotspots on vertically stacked substrates.