Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems

Single-ended static random access memory (SE-SRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a novel six-transistor (6T) SE-SRAM bitcell for low-V-dd and highspeed embedded applications with significant improvement in their power, performance and stability under process variations. The proposed design has a strong 2.65x worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic 'one' is achieved, which is problematic in SE-SRAM cells even at lower voltage. The proposed bitcell design is mainly targeted for word-organized SRAMs. A 16 x 16 x 32 bit SRAM with proposed and standard 6T bitcells is simulated (including parasitics) for 65nm CMOS technology to evaluate and compare the different performance parameters, such as, read SNM, write-ability, access delay and power. The dynamic and leakage power dissipation in the proposed 6T design is reduced by 28% and 21%, respectively, as compared to standard 6T design.