Design and Implementation of Area and Power Efficient Reconfigurable FIR Filter with Low Complexity Coefficients

This paper presents the design and implementation of area and power efficient reconfigurable finite impulse response (FIR) filter. We present a method for designing a reconfigurable filter with low binary complexity coefficients (LBCC) and thus to optimize the filter while satisfying the design specifications. The total number of non zero binary bits is taken as a measure of the binary complexity (BC) of a coefficient. We propose two implementation architectures namely signed-magnitude architecture (SMA) and signed-decimal architecture (SDA) which are based on 3-bit binary common sub expression elimination (BCSE) algorithm and vertical horizontal BCSE (VHBCSE) algorithm respectively. SMA and SDA reduce the redundant computations of the coefficient multiplications in the filter. The proposed filters are synthesized on tsmc 65nm CMOS technology. The synthesis results show that the proposed filters are area and power efficient when compared with the existing ones.