Performance Comparison of Reconfigurable Low Complexity FIR Filter Architectures

This paper compares three architectures of low complexity digital finite impulse response (FIR) filters for high-performance applications. The design of three reconfigurable architectures includes two fully programmable MAC-based filter processor and one dedicated architecture where the filter coefficients are fixed before synthesis. The proposed MAC-based FIR Filter architecture uses two different multipliers for higher order and lower order filters. The multipliers specifically targets on computation re-use in vector-scalar products and can be effectively used in the low complexity programmable FIR filter design. The proposed MAC based filter architecture with different multiplier blocks are capable of operating for different word length filter coefficients at a high speed clock frequency of 109.7 MHz based on Virtex 2v3000ff1152-4 field-programmable gate array.