Design and implementation of cascade decimation filter for radio communications

被引：1
|
作者：
Grati, K [1 ]
Ghazel, A [1 ]
Naviner, L [1 ]
Moatamri, F [1 ]
机构：
[1] UTIC, Ecole Super Commun, El Ghazala 2083, Tunisia
来源：
ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS | 2001年
关键词：
D O I：
10.1109/ICECS.2001.957524
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper describes the design of a decimation filter for use with a 4(th) order band-pass SigmaDelta modulator adapted for multi-standards wireless transceiver. The simulations undertaken demonstrated that GSM and DECT standards specifications are met by a filtering cascade structure composed of 5(th) order comb filter, 2 half-band filter stages and a droop-correction filter. A fixed-point architectural design was defined and low-power FPGA implementation results are reported.
引用
收藏
页码：1603 / 1606
页数：4
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