Opens and delay faults in CMOS RAM address decoders

被引：30
|
作者：
Hamdioui, Said [1 ]
Al-Ars, Zaid [1 ]
de Goor, Ad J. van [1 ]
机构：
[1] Delft Univ Technol, Fac Elect Engn Math & Comp Sci, Comp Engn Lab, NL-2628 CD Delft, Netherlands
来源：
IEEE TRANSACTIONS ON COMPUTERS | 2006年 / 55卷 / 12期
关键词：
memory testing; open defects; address decoder delay faults; addressing methods; BIST; DFT;
D O I：
10.1109/TC.2006.203
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a complete electrical analysis of Address decoder Delay Faults "ADFs" caused by resistive opens in RAMs. A classification between inter and intragate opens is made. A systematic way is introduced to explore the space of possible tests to detect these faults; it is based on generating appropriate sensitizing address transitions and the corresponding sensitizing operation sequences. DFT features are given to facilitate the BIST implementation of the new tests.
引用
收藏
页码：1630 / 1639
页数：10
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