Core design and system-on-a-chip integration

被引：10
|
作者：
Rincon, AM
Cherichetti, C
Monzel, JA
Stauffer, DR
Trick, MT
机构：
[1] IBM Microelectronics Corp, Essex Junction
来源：
IEEE DESIGN & TEST OF COMPUTERS | 1997年 / 14卷 / 04期
关键词：
D O I：
10.1109/54.632878
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
System-on-a-chip (SOC) may take various forms, but three approaches are known: vendor design, partial integration, and desktop. These approaches provide a wide range of design flexibility and time-to-market scenarios. Some IBM designs that cover the spectrum of SOC design approaches are described. Hard cores in the considered designs include a 32-bit PCI, a PowerPC 401 CPU, a memory controller from Rambus, a video PLL (phase-locked loop), a video DAC, and two-high speed SRAMS.
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页码：26 / 35
页数：10
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