Low Cost FPGA based Implementation of a DRFM System

被引：1
|
作者：
Mesarcik, Michael B. [1 ]
O'Hagan, Daniel W. [1 ,2 ]
Paine, Stephen [1 ]
机构：
[1] Univ Cape Town, Cape Town, South Africa
[2] Fraunhofer Inst High Frequency Phys & Radar Tech, Wachtberg, Germany
来源：
2019 IEEE RADAR CONFERENCE (RADARCONF) | 2019年
关键词：
D O I：
10.1109/radar.2019.8835754
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Digital Radio Frequency Memory (DRFM) is a technique used to record an incoming Radio Frequency (RF) signal and apply series of time-delays, amplitude scalings and frequency shifts before retransmitting the signal in an effort to deceive a radar system. This technique is used widely in the electronic defense industry as a form of radar countermeasure by synthesising artificial targets. The design and implementation of a DRFM system on a low cost Field Programmable Gate Array (FPGA) is shown along with an investigation of the performance of the system architecture.
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