Real-time Implementation of Fractal Image Compression in Low Cost FPGA

被引：0
|
作者：
Saad, Abdul-Malik H. Y. [1 ]
Abdullah, Mohd Z. [2 ]
机构：
[1] Univ Sains Malaysia, Sch Elect & Elect Engn, Nibong Tebal Pulau Pinan, Malaysia
[2] Univ Sains Malaysia, Collaborat Microelect Design Excellence Ctr CEDEC, Engn Campus, George Town 14700, Malaysia
来源：
2016 IEEE INTERNATIONAL CONFERENCE ON IMAGING SYSTEMS AND TECHNIQUES (IST) | 2016年
关键词：
ARCHITECTURE;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Fractal Image Compression (FIC) is one of the most popular techniques used in image and video compression due to its simplicity and superior performance. The main drawback of FIC arises from its time consuming operation, especially when a full search is attempted. Hence, it is very challenging to achieve a real-time operation if this algorithm is implemented in general processor unit. In this paper, a new parallel architecture is proposed for implementing a full-search FIC coding. This proposed design is synthesized on a low-cost FPGA and optimized at circuit level in order to achieve a near real-time operation. The performance of the proposed architecture is quantitatively evaluated in terms of run-time, peak-signal-to-noise-ratio (PSNR) and compression efficiency. A run-time equivalent to a video speed of 20 frame per second (fps) is easily achieved on this new hardware with PSNR and compression ratio averaging at 30 dB and 5.82 % respectively.
引用
收藏
页码：13 / 18
页数：6
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