Improving ESD Robustness of Stacked Diodes with Embedded SCR for RF Applications in 65-nm CMOS

被引:0
|
作者
Lin, Chun-Yu [1 ]
Fan, Mei-Lian [2 ]
Ker, Ming-Dou [2 ]
Chu, Li-Wei [3 ]
Tseng, Jen-Chou [3 ]
Song, Ming-Hsiang [3 ]
机构
[1] Natl Taiwan Normal Univ, Dept Appl Elect Technol, Taipei, Taiwan
[2] Natl Chiao Tung Univ, Inst Electron, Hsinchu, Taiwan
[3] Taiwan Semiconductor Manufactur Co, Hsinchu, Taiwan
关键词
Diode; electrostatic discharge (ESD); radio-frequency (RF); silicon-controlled rectifier (SCR); AMPLIFIER; DESIGN;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
To protect the radio-frequency (RF) integrated circuits from the electrostatic discharge (ESD) damage in nanoscale CMOS process, the ESD protection circuit must be carefully designed. In this work, stacked diodes with embedded silicon-controlled rectifier (SCR) to improve ESD robustness was proposed for RF applications. Experimental results in 65-nm CMOS process show that the proposed design can achieve low parasitic capacitance, low turn-on resistance, and high ESD robustness.
引用
收藏
页数:4
相关论文
共 50 条
  • [41] A 25-28Gbps Clock and Data Recovery System with Embedded Equalization in 65-nm CMOS
    Sun, Li
    Pan, Alex
    Wang, Keh Chung
    Yue, C. Patrick
    2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 960 - 963
  • [42] Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process
    Guangyi LU
    Yuan WANG
    Lizhong ZHANG
    Jian CAO
    Xing ZHANG
    Science China(Information Sciences), 2016, 59 (12) : 170 - 178
  • [43] A Compact and Low Power Bandpass Amplifier for Low Bandwidth Signal Applications in 65-nm CMOS
    Noshahr, Fereidoon Hashemi
    Sawan, Mohamad
    2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017,
  • [44] Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process
    Lu, Guangyi
    Wang, Yuan
    Zhang, Lizhong
    Cao, Jian
    Zhang, Xing
    SCIENCE CHINA-INFORMATION SCIENCES, 2016, 59 (12)
  • [45] Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process
    Lu, Guangyi
    Wang, Yuan
    Zhang, Xing
    IEICE TRANSACTIONS ON ELECTRONICS, 2016, E99C (05): : 590 - 596
  • [46] An Injection-Locked Power Up-Converter in 65-nm CMOS for Cellular Applications
    Lindstrand, Jonas
    Tormanen, Markus
    Sjoland, Henrik
    IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2019, 67 (03) : 1065 - 1077
  • [47] A 65-nm CMOS 8-GHz Injection Locked Oscillator for HDR UWB Applications
    Toupe, Romaric
    Deval, Yann
    Badets, Franck
    Begueret, Jean-Baptiste
    ESSCIRC 2008: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2008, : 106 - +
  • [48] Design of a CMOS 65-nm inductor-less VCO for ISM applications in the VHF band
    Gaoding, Ningcheng
    Bousquet, Jean-Francois
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2020, 48 (03) : 309 - 320
  • [49] Two-Port Characterization of Symmetric Varactors in 65-nm CMOS Process for Mixer Applications
    Azmeen-ur-Rahman, Saad
    Hasna, Mazen O.
    Ekin, Sabit
    Choi, Wooyeol
    2023 IEEE TEXAS SYMPOSIUM ON WIRELESS AND MICROWAVE CIRCUITS AND SYSTEMS, WMCS, 2023,
  • [50] A Compact RF Module With Hybrid Stacked Transformer and Integrated Transceiver Switch in 65 nm CMOS Technology
    Chen, Yuting
    Guo, Qing
    Ma, Yue
    Ren, Xingang
    Wu, Bo
    Wang, Gang
    Wu, Xianliang
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2025, 72 (04) : 549 - 553