Design for Test and Diagnosis of Power Switches

被引：0

作者：

Valka, Miroslav ^{[1
]}

Bosio, Alberto ^{[2
]}

Dilillo, Luigi ^{[2
]}

Girard, Patrick ^{[2
]}

Virazel, Arnaud ^{[2
]}

Debaud, Philippe ^{[3
]}

Guilhot, Stephane ^{[3
]}

机构：

[1] Grenoble Alpes Univ, TIMA Lab, Grenoble, France

[2] Univ Montpellier, LIRMM Lab, F-34059 Montpellier, France

[3] ST Microelect, Grenoble, France

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2016年 / 25卷 / 03期

关键词：

Design for test and diagnosis; low power design; power gating; power switches; REDUCTION;

D O I：

10.1142/S0218126616400132

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel Design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. The proposed approach has been validated through SPICE simulations on ITC'99 benchmark circuits as well as on industrial test cases.

引用

页数：18

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