Design of a low latency high speed pipelining multiplier

被引：0

作者：

Wu, YJ ^{[1
]}

Chen, HY ^{[1
]}

Wei, SJ ^{[1
]}

机构：

[1] Tsing Hua Univ, Inst Microelect, Beijing 100084, Peoples R China

来源：

2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ICASIC.2001.982622

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low latency pipelined multiplier architecture using Booth encoding technique is presented in this paper. Based on such architecture, a 16-bit multiplier, with only 5 cycles latency and about 5,000 equivalent logic gates, had been designed and integrated into the DSP core that is a key component of the four-channel CODEC chip. The chip was fabricated in 0.5um double-poly three-metal CMOS technology. Testing results show that the multiplier can work at a more than 100MHz clock frequency.

引用

页码：551 / 554

页数：4

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