ATPG system and fault simulation methods for digital devices

Models and methods of digital circuit analysis for test generation and fault simulation are offered The two-frame cubic algebra for compact description of sequential primitive element (here and further, primitive) inform of cubic coverings is used. Problems of digital circuit testing are formulated as linear equations. The described cubic fault simulation method allows to propagate primitive fault lists from its inputs to outputs; to generate analytical equations for deductive fault simulation of digital circuit at gate, functional and algorithmic description levels; to build compilative and interpretative fault simulators for digital circuit. The fault list cubic coverings (FLCC) allowing to create single sensitization paths are proposed. The test generation method for single stuck-at fault (SSF) detection with usage of FLCC is developed. The means of test generation for digital devices designed in Active-HDL are offered. The input description of design is based on usage of VHDL, Verilog and graphical representation of Finite State Machine (FSM). The obtained tests are used for digital design verification in Active-HDL. For fault coverage evaluation the program implementation of cubic simulation method is used. Copyright (C) 2001 IFAC.