Design and analysis of dopingless 1T DRAM using work function engineered tunnel field effect transistors

被引:6
|
作者
Arun, A. V. [1 ]
Sreelekshmi, P. S. [1 ]
Jacob, Jobymol [2 ]
机构
[1] APJ Abdul Kalam Technol Univ, Model Engn Coll Kochi, Thiruvananthapam 695016, Kerala, India
[2] APJ Abdul Kalam Technol Univ, Coll Engn Poonjar, Thiruvananthapuram, Kerala, India
来源
MICROELECTRONICS JOURNAL | 2022年 / 124卷
关键词
Dopingless DRAM; Tunnel field effect transistor; Band to band tunneling; Retention time; Sense margin; Workfunction engineering; GATE; RETENTION;
D O I
10.1016/j.mejo.2022.105433
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a dopingless DRAM based on work function engineered Tunnel field effect transistor is proposed. Gate metal workfunction engineering is done to enhance ON/OFF current ratio of drain current, thereby improving the sense margin and retention time. Drain electrode is made up of dual metal, so as to suppress ambipolar current. The analysis of dual material gate dual drain electrode DRAM (DMG DDE DRAM) and triple material gate dual drain electrode DRAM (TMG DDE DRAM) is done in terms of retention time and sense margin. The performance parameters with different device dimensions and bias conditions are analyzed. It is observed that the proposed DRAMs work well even when the dimensions are scaled down. In addition, the proposed DRAMs have comparable performance with the conventional DRAMs and provide better performance when compared with other dopingless DRAM. Retention times of 430 ms and 370 ms, sense margins of 130 nA and 101 nA are achieved with TMG DDE DRAM and DMG DDE DRAM respectively.
引用
收藏
页数:7
相关论文
共 46 条
  • [1] Dopingless 1T DRAM: Proposal, Design, and Analysis
    James, Akhil
    Saurabh, Sneh
    IEEE ACCESS, 2019, 7 : 88960 - 88969
  • [2] Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors
    Jeon, Juhee
    Cho, Kyoungah
    Kim, Sangsig
    MICROMACHINES, 2023, 14 (06)
  • [4] 1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design
    Biswas, Arnab
    Ionescu, Adrian M.
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2015, 3 (03): : 223 - 228
  • [5] Design and Analysis of Core-Gate Shell-Channel 1T DRAM
    Ansari, Md Hasan Raza
    Lee, Jae Yoon
    Cho, Seongjae
    Park, Byung-Gook
    2020 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), 2020, : 25 - 26
  • [6] Design and analysis of dual-gate misalignment on the performance of dopingless tunnel field effect transistor
    Deep Shekhar
    Ashish Raman
    Applied Physics A, 2020, 126
  • [7] Design and analysis of dual-gate misalignment on the performance of dopingless tunnel field effect transistor
    Shekhar, Deep
    Raman, Ashish
    APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING, 2020, 126 (06):
  • [8] Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis
    Singh, Shivendra
    Tiwari, Ekta
    Gupta, Abhinav
    Saurabh, Sneh
    PROCEEDINGS OF THE 37TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, VLSID 2024 AND 23RD INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, ES 2024, 2024, : 25 - 30
  • [9] Investigation of Modified 1T DRAM with Twin Gate Tunneling Field Effect Transistor for Improved Retention Characteristics
    Han, Dong Chang
    Jang, Deok Jin
    Lee, Jae Yoon
    Cho, Seongjae
    Cho, Il Hwan
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2020, 20 (02) : 145 - 150
  • [10] Design and performance analysis of gate-all-around negative capacitance dopingless nanowire tunnel field effect transistor
    Solay, Leo Raj
    Kumar, Naveen
    Amin, S. Intekhab
    Kumar, Pradeep
    Anand, Sunny
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2022, 37 (11)