Understanding and modelling the PBTI reliability of thin-film IGZO transistors

被引:35
|
作者
Chasin, A. [1 ]
Franco, J. [1 ]
Triantopoulos, K. [1 ,2 ]
Dekkers, H. [1 ]
Rassoul, N. [1 ]
Belmonte, A. [1 ]
Smets, Q. [1 ]
Subhechha, S. [1 ]
Claes, D. [1 ,2 ]
van Setten, M. J. [1 ]
Mitard, J. [1 ]
Delhougne, R. [1 ]
Afanas'ev, V [1 ,2 ]
Kaczer, B. [1 ]
Kar, G. S. [1 ]
机构
[1] IMEC, Leuven, Belgium
[2] KULeuven, Leuven, Belgium
关键词
D O I
10.1109/IEDM19574.2021.9720666
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We study the impact of the gate-dielectric on the Positive Bias Temperature Instability (PBTI) of IGZO thin-film transistors (TFT). We show that PBTI is controlled by the gate-dielectric pre-existent electron traps and its hydrogen content. The degradation process can be composed of up to four different mechanisms with different time kinetics, voltage acceleration factors and activation energies. A simplified physics-based model is used to reproduce stress and relaxation traces recorded in a wide range of test conditions. Gate-dielectric optimization enables scaled EOT (2.5nm) IGZO TFT to achieve a record lifetime of similar to 1 year continuous operation at 95 degrees C and V-ov = 1V, with a strict failure criterion of vertical bar Delta V-th vertical bar<30mV.
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页数:4
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