A collector-up heterojunction bipolar transistor using a p-type doping buried layer

被引:0
|
作者
Hsu, Hung-tsao [1 ]
Hsin, Yue-ming [1 ]
机构
[1] Natl Cent Univ, Dept Elect Engn, Jhongli 32001, Taiwan
关键词
D O I
10.1088/0268-1242/21/12/039
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we report a collector-up npn heterojunction bipolar transistor (C-up HBT) which employs a p-type doping buried layer inserted between an extrinsic emitter and a subemitter for current confinement. Fabrication of C-up AlGaAs/GaAs HBTs with a selectively buried layer by metalorganic chemical vapour deposition (MOCVD) regrowth is described. The fabricated C-up AlGaAs/ GaAs HBT demonstrates good common-emitter I-V characteristics and a current gain of 18. A systematic analysis is performed to verify the functionality of the p-type doping buried layer using a two-dimensional device simulator. It is found that the p-type doping buried layer should be biased properly to achieve the high efficiency of current confinement. And the HBT with a large Delta E-V at the base-emitter heterojunction is preferred for the proposed C-up HBTs to reduce hole back-injection.
引用
收藏
页码:1728 / 1732
页数:5
相关论文
共 50 条
  • [31] Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer
    Yang, Xiaoming
    Cao, Taiqiang
    Zhang, Xiaohua
    Li, Tianqian
    Luo, Hang
    MICROMACHINES, 2023, 14 (04)
  • [32] Influence of the δ-doping sheet and setback layer on the performance of an InGaP/GaAs heterojunction bipolar transistor
    Cheng, SY
    Pan, HJ
    Shie, YH
    Chen, JY
    Chang, WL
    Wang, WC
    Lin, PH
    Liu, WC
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 1998, 13 (10) : 1187 - 1192
  • [33] GaInP/GaAs collector-up tunnelling-collector heterojunction bipolar transistors with zero-offset and low-knee-voltage characteristics
    Mochizuki, K
    Welty, RJ
    Asbeck, PM
    ELECTRONICS LETTERS, 2000, 36 (03) : 264 - 265
  • [34] LIGHT-EMITTING CHARGE INJECTION TRANSISTOR WITH P-TYPE COLLECTOR
    MASTRAPASQUA, M
    CAPASSO, F
    LURYI, S
    HUTCHINSON, AL
    SIVCO, DL
    CHO, AY
    APPLIED PHYSICS LETTERS, 1992, 60 (19) : 2415 - 2417
  • [35] First fabrication of GaInAs/InP buried metal heterojunction bipolar transistor and reduction of base-collector capacitance
    Arai, Toshiki
    Harada, Yoshimichi
    Yamagami, Shigeharu
    Miyamoto, Yasuyuki
    Furuya, Kazuhito
    Japanese Journal of Applied Physics, Part 2: Letters, 2000, 39 (6 A):
  • [36] First fabrication of GaInAs/InP buried metal heterojunction bipolar transistor and reduction of base-collector capacitance
    Arai, T
    Harada, Y
    Yamagami, S
    Miyamoto, Y
    Furuya, K
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2000, 39 (6A): : L503 - L505
  • [37] Collector junction depletion-layer width model of SiGe heterojunction bipolar transistor with intrinsic SiGe layer
    Hu Hui-Yong
    Shu Yu
    Zhang He-Ming
    Song Jian-Jun
    Xuan Rong-Xi
    Qing Shan-Shan
    Qu Jiang-Tao
    ACTA PHYSICA SINICA, 2011, 60 (01)
  • [39] High-performance, graded-base AlGaAs InGaAs collector-up heterojunction bipolar transistors using a novel selective area regrowth process
    Tseng, HC
    Ye, YZ
    IEEE ELECTRON DEVICE LETTERS, 1999, 20 (06) : 271 - 273
  • [40] Fabrication of InGaP/Al0.98Ga0.02As/GaAs oxide-confined collector-up heterojunction bipolar transistors
    Chen, WB
    Su, YK
    Lin, CL
    Wang, HC
    Chen, SM
    Su, JY
    Wu, MC
    IEEE ELECTRON DEVICE LETTERS, 2003, 24 (10) : 619 - 621