A Novel High Performance Medium -Voltage DEnMOS in 40nm CMOS Technology

被引：0

作者：

Wei, Lin ^{[1
]}

Singh, Upinder ^{[1
]}

Koo, Jeoung Mo ^{[1
]}

Jiang Huihua ^{[1
]}

机构：

[1] GLOBALFOUNDRIES Singapore Pte Ltd, Technol Dev Dept, Singapore, Singapore

来源：

PRODCEEDINGS OF THE 2018 IEEE 30TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD) | 2018年

关键词：

Symmetric Drain Extended MOSFET; 40nm CMOS Technology;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new kind of symmetric medium-voltage DEnMOS embedded in 40nm CMOS process is developed out for parasitic capacitance improvement and specified on resistance decrease by adding one to two masks except for baseline set. Hot carrier induced degradation and DC measurement result are studied. Our results clearly show that the new concept gets tremendous improvement in both on-resistance and parasitic capacitance.

引用

页码：292 / 294

页数：3

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