Formation and mechanism of dimple/pit on Si substrate during WSix/poly-Si gate stack etch

被引：4
|
作者：
Pan, PH
Liu, L
机构：
来源：
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B | 1997年 / 15卷 / 05期
关键词：
D O I：
10.1116/1.589520
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The formation of dimple/pit on gate oxide and Si substrate was observed after WSix/poly-Si gate stack etch. The effects of process step on the formation of dimple/pit have been studied. The key process steps causing the dimple/pit problem are the WSix anneal and the low pressure chemical vapor deposition nitride deposition. The mechanism of dimple/pit has been proposed. The rough WSix/poly interface is the main cause of dimple formation, and the presence of Si clusters in the annealed WSix layer is the key contributor for pits in the Si substrate. A low temperature process (before gate stack etch) was found to be effective to reduce and/or eliminate the dimple/pit problem. (C) 1997 American Vacuum Society. [S0734-211X(97)04405-3].
引用
收藏
页码：1752 / 1757
页数：6
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