Low temperature operation of graded-channel SOI nMOSFETs for analog applications

被引：1
|
作者：
Pavanello, MA
Der Agopian, PG
Martino, JA
Flandre, D
机构：
[1] Univ Sao Paulo, Lab Sistemas Integraveis, BR-05508900 Sao Paulo, Brazil
[2] State Univ Campinas, Ctr Semicond Components, Campinas, Brazil
[3] Univ Catholique Louvain, Microelect Lab, B-1348 Louvain, Belgium
来源：
JOURNAL DE PHYSIQUE IV | 2002年 / 12卷 / PR3期
关键词：
D O I：
10.1051/jp420020030
中图分类号：
O4 [物理学];
学科分类号：
0702 ;
摘要：
We present in this work is an analysis of die low temperature operation of Graded-Channel fully-depleted Silicon-On-Insulator (SOI) nMOSFETs for analog applications. This analysis is supported by a comparison between the results obtained by MEDICI numerical bidimensional simulations and measurements. The Graded-Channel transistor presents higher Early voltage and transconductance at 100 K if compared to the conventional fully-depleted SOI nMOSFET.
引用
收藏
页码：23 / 26
页数：4
相关论文
共 50 条
  • [1] Liquid Helium Temperature Operation of Graded-Channel SOI nMOSFETs
    de Souza, M.
    Kilchytska, V.
    Flandre, D.
    Pavanello, M. A.
    MICROELECTRONICS TECHNOLOGY AND DEVICES - SBMICRO 2012, 2012, 49 (01): : 135 - 144
  • [2] Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
    Pavanello, Marcelo Antonio
    de Souza, Michelly
    Ribeiro, Thales Augusto
    Martino, Joao Antonio
    Flandre, Denis
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2016, 31 (11)
  • [3] Asymmetric Self-Cascode versus Graded-Channel SOI nMOSFETs for Analog Applications
    Assalti, R.
    Pavanello, M. A.
    Flandre, D.
    de Souza, M.
    2015 30TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), 2015,
  • [4] Low-Frequency Noise of Submicron Graded-Channel SOI nMOSFETs at High Temperature
    Molto, A. R.
    Doria, R. T.
    de Souza, M.
    Flandre, D.
    Pavanello, M. A.
    2016 31ST SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), 2016,
  • [5] Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications
    Pavanello, MA
    Der Agopian, PG
    Martino, JA
    Flandre, D
    MICROELECTRONICS JOURNAL, 2006, 37 (02) : 137 - 144
  • [6] The low-frequency noise behaviour of graded-channel SOI nMOSFETs
    Simoen, E.
    Claeys, C.
    Chung, T. M.
    Flandre, D.
    Pavanello, M. A.
    Martino, J. A.
    Raskin, J. -P.
    SOLID-STATE ELECTRONICS, 2007, 51 (02) : 260 - 267
  • [7] Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer
    de Souza, Michelly
    Flandre, Denis
    Pavanello, Marcelo Antonio
    SOLID-STATE ELECTRONICS, 2008, 52 (12) : 1933 - 1938
  • [8] Comparative of analog performance of transcapacitances in asymmetric self-cascode and graded-channel SOI nMOSFETs
    Camila Restani Alves
    Michelly de Souza
    Journal of Computational Electronics, 2023, 22 : 148 - 154
  • [9] Comparative of analog performance of transcapacitances in asymmetric self-cascode and graded-channel SOI nMOSFETs
    Alves, Camila Restani
    de Souza, Michelly
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2023, 22 (01) : 148 - 154
  • [10] On the Origin of Low-Frequency Noise of Submicron Graded-Channel Fully Depleted SOI nMOSFETs
    Molto, A. R.
    Doria, R. T.
    de Souza, M.
    Pavanello, M. A.
    2015 30TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), 2015,
12345