SOI devices for sub-0.1 μm gate lengths

被引：0

作者：

Colinge, JP ^{[1
]}

Park, JT ^{[1
]}

Colinge, CA ^{[1
]}

机构：

[1] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA

来源：

2002 23RD INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Different SOI MOSFET structures for sub 0.1 mum gate lengths are discussed. To reduce short-channel effects such as DIBL and subthreshold slope degradation, thin SOI films have to be used, which causes high source and drain resistance and low threshold voltage problems. These problems can be solved using midgap gate materials, elevated or Schottky S&D structures and multiple gates. The use of ground-plane structures improves the short-channel effects but increase the body effect, while the use of multiple gates (double gate, triple gate, etc.) improves all device characteristics and increase the current drive.

引用

页码：109 / 113

页数：5

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