A sub-mW MPEG-4 motion estimation processor core for mobile video application

被引：1

作者：

Kuroda, Y ^{[1
]}

Miyakoshi, J ^{[1
]}

Miyama, M ^{[1
]}

Imamura, K ^{[1
]}

Hashimoto, H ^{[1
]}

Yoshimoto, M ^{[1
]}

机构：

[1] Kanazawa Univ, Fac Engn, Kanagawa 9208667, Japan

来源：

ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE | 2004年

关键词：

D O I：

10.1109/ASPDAC.2004.1337632

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a sub-mW motion estimation processor core for MPEG4 video encoding. It features a Gradient Descent Search algorithm whose computation power is only 7% of the conventional 1:4-subsampling search, producing higher picture quality. Another feature is an optimized SIMID datapath architecture to decrease a clock frequency and an operating voltage. It has been fabricated with CMOS 5-metal 0.18 um technology. The measured power consumption to process a QCIF 15 fps video is 0.4 mW under 0.85 MHz@1.0

引用

页码：527 / 528

页数：2

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