Measurements of gate-oxide interface roughness in strained-Si virtual substrate SiGe/Si MOSFET device structures

A series of SiGe/Si virtual substrate based n-channel Si MOSFETs have been analysed using transmission electron microscopy (TEM). The focal point of this work is to investigate the effect of gate oxidation upon an undulating virtual substrate surface. We find that cross-sectional TEM images of devices processed on such a wafer show a significant difference in the amplitude of gate-oxide interface roughness at the sloping edges of substrate surface. Moreover, such nanoscale roughening correlates to the variable vicinal nature of the undulating SiGe substrate surface. Methods for quantitative measurement of the roughness are presented.