Interface Engineering for High-k/Ge Gate Stack

被引：0
|
作者：
Xie, Ruilong [1 ]
Zhu, Chunxiang [1 ]
机构：
[1] Natl Univ Singapore, Dept Elect & Comp Engn, SNDL, Singapore 117576, Singapore
来源：
2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4 | 2008年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, various interface engineering techniques for high-k/Ge gate stack for advanced CMOS device applications are reviewed. High-k gate stack formation on Ge substrate is first addressed with emphasis on pre-gate surface passivation. Post gate dielectric (post-gate) treatments are then discussed to further improve the high-k/Ge interface quality.
引用
收藏
页码：1244 / 1247
页数：4
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