Compensation of a winner take all circuit

被引：0
|
作者：
Kothapalli, G [1 ]
机构：
[1] Edith Cowan Univ, Perth, WA 6027, Australia
来源：
ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | 2003年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Design and simulation results of CMOS winner-take-all circuit are presented. A 16-cell test circuit has been designed for intended implementation in 0.18 mum CMOS process. This paper describes the architecture and design issues related to a CMOS WTA circuit. Several design issues such as high resolution, high speed, low power consumption, compactness, and high input voltage range have been addressed. The proposed circuit has a compact configuration of complexity O(N) where N denotes input count. It seems to be very suitable, especially for charge-based applications where input vectors are generated by a set of charged capacitances.
引用
收藏
页码：352 / 355
页数：4
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