Analyze jitter to improve high-speed

被引：8

作者：

Lauterbach, M ^{[1
]}

Wey, T

机构：

[1] LeCroy Corp, Prod Management, Chestnut Ridge, NY USA

[2] Amer Microsyst Inc, Timing Generator Prod Grp, Lower Gwynedd, PA USA

来源：

IEEE SPECTRUM | 2000年 / 37卷 / 07期

关键词：

D O I：

10.1109/6.852054

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Knowing the source of jitter is especially crucial to high-speed circuit design. Jitter describes an intermittent variation of a signal from its ideal position. In particular, it includes instability in signal timing characteristics such as period, frequency, and phase. Such variations may intrude on a cycle-to-cycle basis or over longer periods.

引用

页码：62 / 67

页数：6

共 50 条

[41] Reducing Intercarrier Interference in High-Speed OFDM Systems in Presence of Jitter Noise
Sharief, A. H.
Ram, M. Satya Sai
[J]. INNOVATIONS IN ELECTRONICS AND COMMUNICATION ENGINEERING, 2019, 33 : 299 - 317
[42] Comparison of Jitter Decomposition Methods for BER Analysis of High-Speed Serial Links
Erb, Stefan
Pribyl, Wolfgang
[J]. PROCEEDINGS OF THE 13TH IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2010, : 370 - 375
[43] On-chip jitter-spectrum-analyzer for high-speed digital designs
Takamiya, M
Inohara, H
Mizuno, M
[J]. 2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 : 350 - 351
[44] Modeling and analysis techniques of jitter enhancement across high-speed interconnect systems
Beyene, Wendemagegnehu Wendem
[J]. ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2007, : 29 - 32
[45] Jitter Analysis and Decomposition Based on EMD/HHT in High-Speed Serial Communications
Zhu, Jian
Huang, Wei
[J]. IEEE CIRCUITS AND SYSTEMS INTERNATIONAL CONFERENCE ON TESTING AND DIAGNOSIS, 2009, : 462 - 465
[46] The Instrument Bandwidth Effect in Jitter and BER Test for High-Speed Serial Interconnection
Yang Jun-Feng
Song Ke-Zhu
Cao Ping
[J]. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2013, 61 (01) : 256 - 262
[47] A New Method to Estimate Phases of Sinusoidal Jitter to Evaluate High-Speed Links
Chang, Yu
Madden, Chris
Schmitt, Ralf
[J]. 2011 IEEE 20TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2011, : 227 - 230
[48] Efficient Statistical Simulation of Intersymbol Interference and Jitter in High-Speed Serial Interfaces
Cristofoli, Andrea
Palestri, Pierpaolo
Da Dalt, Nicola
Selmi, Luca
[J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2014, 4 (03): : 480 - 489
[49] Design a low-jitter clock for high-speed data converters system
Li, YK
Zhang, GR
Tian, QM
[J]. ISTM/2005: 6th International Symposium on Test and Measurement, Vols 1-9, Conference Proceedings, 2005, : 546 - 548
[50] Design and analysis of XOR gates for high-speed and low-jitter applications
Bui, Hung Tien
Savaria, Yvon
[J]. WMSCI 2005: 9TH WORLD MULTI-CONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL 6, 2005, : 60 - 65

← 1 2 3 4 5 →